1. Field of the Invention
This invention relates to MOSFET devices and more particularly to prevention of latchup problems therein.
2. Description of Related Art
U.S. Pat. No. 4,927,777 of Hsu et al "Method of Making a MOS Transistor" shows forming trenches about wells of oppositely doped material with insulating material.
U.S. Pat. No. 4,960,726 of Lechaton et al "BICMOS Process" describes deep trenches which are lined with an insulating material such as silicon dioxide and filled with a "filler material" such as polysilicon or an insulator. There are shallow trench structures comprising an insulating material such as silicon dioxide or intrinsic polysilicon.
U.S. Pat. No. 5,071,777 of Gahle "Method of Fabricating Implanted Wells and Islands of CMOS Circuits" protection against latch-up is provided by edge regions which are thermally oxidized to form a field oxide layer.
U.S. Pat. No. 5,096,843 of Kodaira "Method of Manufacturing a Bipolar CMOS Device" employs a trench filled with material formed on the side wall of the trench serving as a barrier against impurities.
U.S. Pat. No. 5,137,837 of Chang et al "Radiation-Hard High-Voltage Semiconductive Device Structure Fabricated on SOI Substrate" and U.S. Pat. No. 5,158,900 of Lau et al "Method of Separately Fabricating a Base/Emitter Structure of a BiCMOS Device" show methods/structures for isolating bipolar, NMOS and PMOS devices within an integrated circuit structure.
Latch-up is a malfunction of MOSFET devices which presents a problem in the design of CMOS integrated circuits. Several solutions have been recommended in the past. One is the use of epitaxial wafers which is not cost effective. Another solution is enlargement of N+ device and P+ device spacing, which will enlarge the die size which is undesirable where smaller size is more desirable. The minority carrier should be recombined in the enlarged spacing, the substrate current I.sub.b (FIG. 1) could be reduced.
An object of the instant invention is to reduce the die size, enhance the immunity to latchup, and provide greater cost effectiveness.
Latchup Mechanism
FIG. 1 shows a physics and lumped circuit model illustrating problem of the latchup mechanism of a CMOS device. The schematic and equivalent circuits of parasitic resistors R.sub.S 35 and R.sub.W 36 and parasitic NPN and PNP bipolar transistors 27 and 31 in the CMOS are drawn as equivalent discrete devices. The CMOS device is formed on a P- doped substrate 10. The bias V.sub.SS is connected by line 25 to lines 8 and 9 which are connected to P+ region 11 and N+ region 12. N+ region 12 is the source of an FET device 5 comprising gate 14 (connected by line 17 to V.sub.IN, and completed by the drain in the form of an N+ region 13 connected by line 16 to V.sub.OUT, The emitter of NPN equivalent transistor 27 is connected to source region 12 from internally of the substrate 10. The collector of transistor 27 is connected by line 28 to the base of PNP transistor 31 which is shown within the n-well tub 30 in which the other, adjacent FET device 6 is located. The base of transistor 27 is connected to line 38 which connects to one end of equivalent R.sub.S resistor 36, the other end of which is connected to the P+ region 11. Line 38 is also connected via line 34 in well 30 to the collector of transistor 31, the emitter of which is connected via line 33 to P+ region 20 which is the drain of the FET 6, which is biased by V.sub.DD source 22 through line 22. V.sub.DD is connected via line 7 to N+ region 23 as well, which is connected to one end of R.sub.W which is connected to the base of PNP transistor 31.
A mathematical analysis of the relationships shown by the lumped circuit model of FIG. 1 is set forth below: EQU .beta..sub.npn, .beta..sub.pnp : common-emitter current gain
positive feedback condition: EQU (I.sub.b .beta..sub.npn IRw).beta..sub.pnp -I.sub.RS &gt;I.sub.b
R.sub.S =shunting resistance PA1 .beta.=device transconductance parameter PA1 I.sub.RS =current through shunting resistance PA1 I.sub.b =current to base of a "parasitic" npn bipolar transistor EQU I.sub.b (.beta..sub.npn .beta..sub.pnp -1)&gt;I.sub.RS +I.sub.RW .beta..sub.pn p PA1 R.sub.W =Well Resistance PA1 I.sub.DD =I.sub.RS +I.sub.b (.beta..sub.npn +1) ##EQU1## Known methods of avoiding latchup: PA1 a) lightly doping a semiconductor substrate, PA1 b) forming wells within the substrate doped with an opposite value dopant, PA1 c) forming a plurality of doped regions within the surface of the substrate and within the surface of the wells, PA1 d) opening trenches along the periphery of the wells, and PA1 e) filling the trenches with a relatively highly conductive material.
I.sub.b can be expressed in terms of total supply current I.sub.DD
1. Reducing the bipolar gain (.beta..sub.npn .beta..sub.pnp)
2. Lowering the shunting resistances (R.sub.S and R.sub.W) Additional relevant factors are as follows:
1. Reduction of the bipolar gain degrades the performance of the FET device.
2. Lowering the R.sub.S (shunting resistance) by using an epitaxial wafer leads to high cost.
3. Lowering the R.sub.W shunting resistance is a good approach.
FIG. 2 shows a partially three dimensional layout of an MOSFET device to illustrate a potential latchup path typical of prior art devices.
In a semiconductor substrate 40 which is doped with P dopant, an N- well 41 contains an N+ structure 42 comprising an N+ well pick-up. Parallel to structure 42 is a P+ structure 43. The structures 42 and 43 are connected to voltage source V.sub.CC. Adjacent to well 41 extending transversely with respect to the direction of structures 42 and 43 is a structure 44 composed of N+ dopant. Structure 44 is connected to bias source V.sub.SS. A V.sub.CC to V.sub.SS path is formed by P+ structure 43, an N- well 41, a P- sub 40, and N+ structure 44, referred to hereinafter as an "SCR" path.
To the right side of FIG. 2, a two dimensional view of an N+ region 47 another N- well 50 is shown with a P+ region 48 connected via line 46 to V.sub.I/O and a N+ region 49 connected to V.sub.CC. A number of electrons are shown in the bulk of the substrate 40 adjacent to N+ region 47. Negative charge 52 is referred to as a minority carrier injection into N- well 50 which has the effect when the V.sub.I/O undershooting below the P- (V.sub.SS, the minority carrier (electron) injected from the N+ to the P- (substrate.) An electron 51 is shown approaching the N- well 41 and it indicates the need to insert a conductive guard structure in accordance with this invention. The electrons form the substrate current. The conductive guard ring structure must be inserted between the N+ region 47 and the N- well 41 to collect the electrons.
FIG. 3A shows a prior art P- semiconductor substrate 55 with a conventional approach to the problem of latchup wherein a space of 100 .mu.m is provided between the N+ region 60 and the N-well 56 to the right. N+ regions 60 and 61 are shown in the P- substrate connected to I/O and V.sub.DD respectively. In the N- well 56 the N+ regions 62, 64 and P+ region 63 are connected respectively to V.sub.dd. The N+ region 66 and the P+ region 68 are both connected by line 69 to V.sub.SS. The N+ region 61 which is connected to source V.sub.DD is the guard ring structure to collect the electrons to avoid going through the resistor 58 and the resistor 59. The voltage drop in the resistor will turn on the P+/N- well to form the P+ region 63, N- well 56, P- substrate 55, N+ region 66 SCR path. The guard ring structure efficiency is poor which cannot collect most of the electron path where the resistor 58 and resistor 59 are shown in the possible electron paths.
FIG. 3B shows a prior art P- semiconductor substrate 75 with an N-well guard ring structure approach to the problem of latchup. The N+ region 80 is shown in the P- substrate connected to I/O, but unlike FIG. 3A, the N+ region 81 is in a new N- well 77 of its own connected to V.sub.DD. In the N- well 76 the N+ regions 82, 84 and P+ region 83 are connected. The guard ring structure efficiency for the N+ region 81 in an N- well 77 is better than when it is N+ only. The resistor 79 is the possible electron path which decreases the conductivity provided by the resistors 58 and 59 which are shown in FIG. 3A.